Le Codeur Fec MFSK

© 2000 Nino Porcino IZ8BLY & M. Greenman ZL1BPU

Ver 1.0, 11 July 2000

Grateful thanks à Phil KA9Q pour les algorithmes et les routines du décodeur Viterbi. Consultez de temps en temps le site web de KA9Q for lots of good stuff sur les codeurs et décodeurs.

Le codeur FEC MFSK (également utilisé dans le programme de IZ8BLY pour le PSK63F) consiste en un   codeur convolutionel et séquentiel de  Rate R = 1/2, with a Constraint Length K = 7.

En conséquence, for every input data bit there are two output data "dibits", generated by two polynomials from the taps of a 7 stage shift register. Call the outputs of these registers O1 to O7. The polynomials are each the modulo 2 sum (XOR) of five of these register outputs. The polynomials are:

Dibit1 = O1 + O3 + O4 + O6 + O7

Dibit2 = O1 + O2 + O3 + O4 + O7

The dibits defined above are multiplexed into a single data stream, in order Dibit1 then Dibit2. They are then transmitted sequentially in a data stream that is coded by bit weight into MFSK symbols, with the first arriving bit given maximum weight. No specific fixed bit weight is given to either dibit, which would allow easy identification at the receiver decoder. Thus the bit weight of each dibit is uncertain; all that can be said is that in the resulting bit stream at the receiver, Dibit1 precedes Dibit2.

The reason for this approach is flexibility: this technology is intended for anywhere from 1 to 5 or more bits per symbol.

Le  décodeur FEC est de type Viterbi . As mentioned, there is no fixed relationship between the coder dibits and the bit weighting of the MFSK symbol (or the PSK63F dibits, which are on the same data stream), and so the decoder must decide from the results whether it has the correct order of dibits. There are two choices - Dibit1 then Dibit2 (correct), or Dibit2 of one bit then Dibit1 of the next (incorrect).

One technique for solving this ambiguity is to use two short "trial decoders" and use the metrics from these to decide which of the two ambiguous alternatives gives the best result, and therefore the order in which the dibits must be used for the full-length decoder.

Le codeur FEC est suivi (en MFSK seulement) par un entrelaceur. Lire la Description de l'Entrelaceur pour plus de détails. L'entrelaceur est a simple diagonal 10 stage concatenated n-bit interleaver, où n est le nombre de  bits représentés par le symbole MFSK .